Z8F082ASH020SC Datasheet, PDF (200/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
182
Assembly
Mnemonic
LDC dst, src
LDCI dst, src
LDE dst, src
LDEI dst, src
LDWX dst, src
LDX dst, src
LEA dst, X(src)
MULT dst
NOP
Flags Notation:
Table 116. eZ8 CPU Instruction Summary (Continued)
Symbolic Operation
Address Mode _Opcode(s)
Flags
Fetch Instr.
dst src
(Hex) C Z S V D H Cycles Cycles
dst ← src
r
Irr
C2
––––– – 2
5
Ir
Irr
C5
2
9
Irr
r
D2
2
5
dst ← src
r←r+1
rr ← rr + 1
Ir
Irr
Irr
Ir
C3
––––– – 2
9
D3
2
9
dst ← src
r
Irr
82
––––– – 2
5
Irr
r
92
2
5
dst ← src
r←r+1
rr ← rr + 1
Ir
Irr
Irr
Ir
83
––––– – 2
9
93
2
9
dst ← src
ER ER
1FE8 – – – – – – 5
4
dst ← src
r
ER
84
––––– – 3
2
Ir
ER
85
3
3
R IRR
86
3
4
IR IRR
87
3
5
r X(rr)
88
3
4
X(rr) r
89
3
4
ER
r
94
3
2
ER
Ir
95
3
3
IRR R
96
3
4
IRR IR
97
3
5
ER ER
E8
4
2
ER IM
E9
4
2
dst ← src + X
r
X(r)
98
––––– – 3
3
rr X(rr)
99
3
5
dst[15:0] ←
RR
dst[15:8] * dst[7:0]
F4
––––– – 2
8
No operation
0F
––––– – 1
2
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024705-0405
PRELIMINARY
eZ8 CPU Instruction Set