Z8F082ASH020SC Datasheet, PDF (222/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
204
UART Timing
Figure 35 and Table 130 provide timing information for UART pins for the case where
CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit
data register has been loaded with data prior to CTS assertion.
CTS
(Input)
DE
(Output)
T3
T1
TXD
(Output)
bit 7 parity stop
end of
stop bit(s)
start bit 0
bit 1
T2
Figure 35. UART Timing With CTS
Parameter
UART
T₁
T₂
T₃
Table 130. UART Timing With CTS
Abbreviation
Delay (ns)
Minimum Maximum
CTS Fall to DE output delay
2 * XIN
period
DE assertion to TXD falling edge (start bit) delay ± 5
End of Stop Bit(s) to DE deassertion delay
±5
2 * XIN period
+ 1 bit time
PS024705-0405
PRELIMINARY
Electrical Characteristics