Z8F082ASH020SC Datasheet, PDF (71/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
53
IRQ0 Enable High and Low Bit Registers
Table 35 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters (Tables 36 and 37) form a priority encoded enabling for interrupts in the Interrupt
Request 0 register. Priority is generated by setting bits in each register.
Table 35. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0–7.
Table 36. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
RESET
R/W
ADDR
7
Reserved
0
R/W
6
T1ENH
0
R/W
5
T0ENH
0
R/W
4
3
2
1
0
U0RENH U0TENH Reserved Reserved ADCENH
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
FC1H
Reserved—Must be 0.
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Table 37. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
FIELD
RESET
R/W
ADDR
7
Reserved
0
R
6
T1ENL
0
R/W
5
T0ENL
0
R/W
Reserved—Must be 0.
4
3
2
1
0
U0RENL U0TENL Reserved Reserved ADCENL
0
0
0
0
0
R/W
R/W
R
R
R/W
FC2H
PS024705-0405
PRELIMINARY
Interrupt Controller