Z8F082ASH020SC Datasheet, PDF (91/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
73
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Reload value.
In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit
Compare value.
Table 49. Timer 0–1 Reload High Byte Register (TxRH)
7
6
5
4
3
2
1
0
TRH
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F02H, F0AH
Table 50. Timer 0–1 Reload Low Byte Register (TxRL)
7
6
5
4
3
2
1
0
TRL
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F03H, F0BH
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to 0001H. In Compare mode, these
two bytes form the 16-bit Compare value.
Timer 0-1 PWM High and Low Byte Registers
The Timer 0-1 PWM High and Low Byte (TxPWMH and TxPWML) registers (Tables 51
and Table 52) control Pulse-Width Modulator (PWM) operations. These registers also
store the Capture values for the CAPTURE and CAPTURE/COMPARE modes.
Table 51. Timer 0–1 PWM High Byte Register (TxPWMH)
BITS
7
6
5
4
3
2
1
0
FIELD
PWMH
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
F04H, F0CH
PS024705-0405
PRELIMINARY
Timers