Z8F082ASH020SC Datasheet, PDF (39/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
21
Operating Mode
NORMAL or HALT
modes
STOP mode
Table 9. Reset Sources and Resulting Reset Type
Reset Source
Special Conditions
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage
Out
exceeds POR level
Watch-Dog Timer time-out
when configured for Reset
None
RESET pin assertion
All reset pulses less than three system clocks
in width are ignored.
On-Chip Debugger initiated Reset System Reset, except the On-Chip Debugger
(OCDCTL[0] set to 1)
is unaffected by the reset
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage
Out
exceeds POR level
RESET pin assertion
All reset pulses less than the specified analog
delay are ignored. See “Electrical
Characteristics” on page 191.
DBG pin driven Low
None
Power-On Reset
Each device in the Z8 Encore! XP^® F08xA Series contains an internal Power-On Reset
(POR) circuit. The POR circuit monitors the supply voltage and holds the device in the
Reset state until the supply voltage reaches a safe operating level. After the supply voltage
exceeds the POR voltage threshold (V_POR), the device is held in the Reset state until the
POR Counter has timed out. If the crystal oscillator is enabled by the option bits, this tim-
eout is longer.
After the ZZ8 Encore! XP^® F08xA Series device exits the Power-On Reset state, the eZ8
CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Watch-
Dog Timer Control (WDTCTL) register is set to 1.
Figure 4 illustrates Power-On Reset operation. Refer to the “Electrical Characteristics” on
page 191 for the POR threshold voltage (V_POR).
PS024705-0405
PRELIMINARY
Reset and STOP Mode Recovery