Z8F082ASH020SC Datasheet, PDF (74/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
56
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
Table 43. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS
FIELD
RESET
R/W
ADDR
7
0
R/W
6
5
Reserved
0
0
R/W
R/W
4
3
C3ENL
0
0
R/W
R/W
FC8H
2
C2ENL
0
R/W
1
C1ENL
0
R/W
0
C0ENL
0
R/W
Reserved—Must be 0.
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 44) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port A or Port D input
pin.
Table 44. Interrupt Edge Select Register (IRQES)
BITS
FIELD
RESET
R/W
ADDR
7
IES7
0
R/W
6
IES6
0
R/W
5
IES5
0
R/W
4
3
IES4
IES3
0
0
R/W
R/W
FCDH
2
IES2
0
R/W
1
IES1
0
R/W
0
IES0
0
R/W
IESx—Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx.
1 = An interrupt request is generated on the rising edge of the PAx input PDx.
where x indicates the specific GPIO Port pin number (0 through 7).
Shared Interrupt Select Register
The Shared Interrupt Select (IRQSS) register (Table 45) determines the source of the
PADxS interrupts. The Shared Interrupt Select register (Table 45) selects between Port A
and alternate sources for the individual interrupts.
PS024705-0405
PRELIMINARY
Interrupt Controller