Z8F082ASH020SC Datasheet, PDF (221/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
203
On-Chip Debugger Timing
Figure 34 and Table 129 provide timing information for the DBG pin. The DBG pin tim-
ing specifications assume a 4ns maximum rise and fall time.
TCLK
XIN
T1
DBG
(Output)
DBG
(Input)
T2
Output Data
T3
T4
Input Data
Figure 34. On-Chip Debugger Timing
Parameter
DBG
T₁
T₂
T₃
T₄
Table 129. On-Chip Debugger Timing
Abbreviation
Delay (ns)
Minimum Maximum
XIN Rise to DBG Valid Delay
XIN Rise to DBG Output Hold Time
DBG to XIN Rise Input Setup Time
DBG to XIN Rise Input Hold Time
–
15
2
–
5
–
5
–
PS024705-0405
PRELIMINARY
Electrical Characteristics