Z8F082ASH020SC Datasheet, PDF (75/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
57
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
Table 45. Shared Interrupt Select Register (IRQSS)
BITS
7
6
5
4
3
2
1
0
FIELD ^{Reserved PA6CS}
Reserved
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FCEH
PA6CS—PA6/Comparator Selection
0 = PA6 is used for the interrupt for PA6CS interrupt request.
1 = The Comparator is used for the interrupt for PA6CS interrupt request.
Reserved—Must be 0.
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 46) contains the master enable bit for all
interrupts.
Table 46. Interrupt Control Register (IRQCTL)
BITS
FIELD
RESET
R/W
ADDR
7
6
5
4
3
2
1
0
IRQE
Reserved
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
FCFH
IRQE—Interrupt Request Enable
This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct regis-
ter write of a 0 to this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0.
PS024705-0405
PRELIMINARY
Interrupt Controller