Z8F082ASH020SC Datasheet, PDF (202/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
184
Assembly
Mnemonic
RRC dst
Table 116. eZ8 CPU Instruction Summary (Continued)
Symbolic Operation
D7 D6 D5 D4 D3 D2 D1 D0
C
dst
Address Mode _Opcode(s)
Flags
Fetch Instr.
dst src
(Hex) C Z S V D H Cycles Cycles
R
C0
****–– 2
2
IR
C1
2
3
SBC dst, src
SBCX dst, src
SCF
SRA dst
dst ← dst – src - C
r
r
r
Ir
R
R
R
IR
R
IM
IR
IM
dst ← dst – src - C
ER ER
ER IM
C←1
R
D7 D6 D5 D4 D3 D2 D1 D0
C
IR
dst
32
****1* 2
3
33
2
4
34
3
3
35
3
4
36
3
3
37
3
4
38
****1* 4
3
39
4
3
DF
1–––– – 1
2
D0
* **0–– 2
2
D1
2
3
SRL dst
0
D7 D6 D5 D4 D3 D2 D1 D0
C
R
dst
IR
1F C0 * * 0 * – – 3
2
1F C1
3
3
SRP src
RP ← src
IM
01
––––– – 2
2
STOP
STOP Mode
6F
––––– – 1
2
SUB dst, src
dst ← dst – src
r
r
22
****1* 2
3
r
Ir
23
2
4
R
R
24
3
3
R
IR
25
3
4
R
IM
26
3
3
IR
IM
27
3
4
SUBX dst, src
dst ← dst – src
ER ER
28
****1* 4
3
ER IM
29
4
3
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024705-0405
PRELIMINARY
eZ8 CPU Instruction Set