Z8F082ASH020SC Datasheet, PDF (199/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
181
Assembly
Mnemonic
HALT
INC dst
INCW dst
IRET
JP dst
JP cc, dst
JR dst
JR cc, dst
LD dst, rc
Flags Notation:
Table 116. eZ8 CPU Instruction Summary (Continued)
Symbolic Operation
Address Mode _Opcode(s)
Flags
Fetch Instr.
dst src
(Hex) C Z S V D H Cycles Cycles
Halt Mode
7F
––––– – 1
2
dst ← dst + 1
R
20
–**––– 2
2
IR
21
2
3
r
0E-FE
1
2
dst ← dst + 1
RR
A0
–***–– 2
5
IRR
A1
2
6
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
SP ← SP + 2
IRQCTL[7] ← 1
BF
***** * 1
5
PC ← dst
DA
8D
––––– – 3
2
IRR
C4
2
3
if cc is true
PC ← dst
DA
0D-FD – – – – – – 3
2
PC ← PC + X
DA
8B
––––– – 2
2
if cc is true
DA
PC ← PC + X
0B-FB – – – – – – 2
2
dst ← src
r
IM
0C-FC – – – – – – 2
2
r
X(r)
C7
3
3
X(r)
r
D7
3
4
r
Ir
E3
2
3
R
R
E4
3
2
R
IR
E5
3
4
R
IM
E6
3
2
IR
IM
E7
3
3
Ir
r
F3
2
3
IR
R
F5
3
3
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024705-0405
PRELIMINARY
eZ8 CPU Instruction Set