Z8F082ASH020SC Datasheet, PDF (168/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
150
RS-232 TX
RS-232 RX
RS-232
Transceiver
VDD
Open-Drain
Buffer
10KOhm
DBG Pin
Figure 23.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
DEBUG Mode
The operating characteristics of the devices in DEBUG mode are:
• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute
specific instructions
• The system clock operates unless in STOP mode
• All enabled on-chip peripherals operate unless in STOP mode
• Automatically exits HALT mode
• Constantly refreshes the Watch-Dog Timer, if enabled
Entering DEBUG Mode
• The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint) instruc-
tion.
• If the DBG pin is held Low during the most recent clock cycle of system reset, the part
enters DEBUG mode upon exiting system reset.
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
• Clearing the DBGMODE bit in the OCD Control Register to 0.
• Power-on reset
• Voltage Brown-Out reset
• Watch-Dog Timer reset
PS024705-0405
PRELIMINARY
On-Chip Debugger