Z8F082ASH020SC Datasheet, PDF (180/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
162
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watch-Dog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the oscillator control register.
The internal precision oscillator is enabled by default. If the user code changes to a differ-
ent oscillator, it may be appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
Clock Failure Detection and Recovery
Primary Oscillator Failure
The Z8 Encore! XP^® F08xA Series devices can generate non-maskable interrupt-like
events when the primary oscillator fails. To maintain system function in this situation, the
clock failure recovery circuitry automatically forces the Watch-Dog Timer oscillator to
drive the system clock. The Watch-Dog Timer oscillator must be enabled to allow the
recovery. Although this oscillator runs at a much slower speed than the original system
clock, the CPU continues to operate, allowing execution of a clock failure vector and soft-
ware routines that either remedy the oscillator failure or issue a failure alert. This auto-
matic switch-over is not available if the Watch-Dog Timer is the primary oscillator. It is
also unavailable if the Watch-Dog Timer oscillator is disabled, though it is not necessary
to enable the Watch-Dog Timer reset function outlined in the Watch-Dog Timer chapter of
this document on page 79.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1KHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but non-failing clock can generate a failure condition. Under
these conditions, do not enable the clock failure circuitry (POFEN must be deasserted in
the OSCCTL register).
Watch-Dog Timer Failure
In the event of a Watch-Dog Timer oscillator failure, a similar non-maskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watch-Dog Timer failure, it is no longer possible to detect a
primary oscillator failure. The failure detection circuitry does not function if the Watch-
Dog Timer is used as the primary oscillator or if the Watch-Dog Timer oscillator has been
disabled. For either of these cases, it is necessary to disable the detection circuitry by deas-
serting the WDFEN bit of the OSCCTL register.
The Watch-Dog Timer oscillator failure detection circuit counts system clocks while look-
ing for a Watch-Dog Timer clock. The logic counts 8004 system clock cycles before deter-
mining that a failure has occurred. The system clock rate determines the speed at which
PS024705-0405
PRELIMINARY
Oscillator Control