Z8F082ASH020SC Datasheet, PDF (12/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
xii
List of Figures
Figure 1. Z8 Encore! XP“ F08xA Series Block Diagram . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8 Encore! XP“ F08xA Series in 20-Pin SOIC, SSOP or PDIP Package
8
Figure 3. Z8 Encore! XP“ F08xA Series in 28-Pin SOIC, SSOP or PDIP Package
8
Figure 4. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 8. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 9. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 10. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . 86
Figure 11. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . 86
Figure 12. UART Asynchronous MULTIPROCESSOR Mode Data Format . . . 90
Figure 13. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
92
Figure 14. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . 94
Figure 15. Infrared Data Communication System Block Diagram . . . . . . . . . 104
Figure 16. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 17. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 18. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . 109
Figure 19. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 20. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . 129
Figure 21. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface
(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 23. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface
(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 24. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
PS024705-0405
PRELIMINARY
List of Figures