Z8F082ASH020SC Datasheet, PDF (22/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
4
CPU and Peripheral Overview
eZ8 CPU Features
The eZ8 CPU, ZiLOG^®’s latest 8-bit Central Processing Unit (CPU), meets the continuing
demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a
superset of the original Z8^® instruction set. The eZ8 CPU features include:
• Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program memory
• Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
• Compatible with existing Z8^® code
• Expanded internal Register File allows access of up to 4KB
• New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
• Pipelined instruction fetch and execution
• New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
• New instructions support 12-bit linear addressing of the Register File
• Up to 10 MIPS operation
• C-Compiler friendly
• 2 to 9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail-
able for download at www.zilog.com.
General Purpose I/O
The Z8 Encore! XP^® F08xA Series features 6 to 25 port pins (Ports A–D) for general pur-
pose I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is
individually programmable.
Flash Controller
The Flash Controller programs and erases Flash memory. The Flash Controller supports
protection against accidental program and erasure.
PS024705-0405
PRELIMINARY
Overview