Z8F082ASH020SC Datasheet, PDF (103/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Seriess
Product Specification
85
RXD
Parity Checker
Receive Shifter
Receiver Control
with Address Compare
Receive Data
Register
System Bus
Control Registers
Transmit Data
Register
Status Register
Baud Rate
Generator
TXD
Transmit Shift
Register
Parity Generator
Transmitter Control
CTS
DE
Figure 9.UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit can be added to the data stream. Each character begins with
an active Low Start bit and ends with either 1 or 2 active High Stop bits. Figures 10 and
11 illustrates the asynchronous data format employed by the UART without parity and
with parity, respectively.
PS024705-0405
PRELIMINARY
UART