Z8F082ASH020SC Datasheet, PDF (42/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
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and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a
pulse four cycles in duration always triggers a reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP^® F08xA Series devices
remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-
tus bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1.
External Reset Indicator
During System Reset or when enabled by the GPIO logic (see See “Port A–D Control Reg-
isters” on page 38.), the RESET pin functions as an open-drain (active low) reset mode
indicator in addition to the input functionality. This reset output feature allows an Z8
Encore! XP^® F08xA Series device to reset other components to which it is connected,
even if that reset is caused by internal sources such as POR, VBO or WDT events.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 8 has elapsed.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The RST bit automatically clears during the system
reset. Following the system reset the POR bit in the WDT Control register is set.
STOP Mode Recovery
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the
chapter “Low-Power Modes” on page 28 for detailed STOP mode information. During
STOP Mode Recovery, the CPU is held in reset for 66 IPO cycles if the crystal oscillator is
disabled or 5000 cycles if it is enabled.
STOP Mode Recovery does not affect onchip registers other than the Watchdog Timer
Control register (WDTCTL) and the Oscillator Control register (OSCCTL). After any
STOP Mode Recovery, the IPO is enabled and selected as the system clock. If another sys-
tem clock source is required or IPO disabling is required, the STOP Mode Recovery code
must reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following STOP Mode Recovery, the STOP bit in the Watch-Dog Timer Con-
PS024705-0405
PRELIMINARY
Reset and STOP Mode Recovery