Z8F082ASH020SC Datasheet, PDF (197/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
179
Table 116. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
Symbolic Operation
Address Mode _Opcode(s)
Flags
Fetch Instr.
dst src
(Hex) C Z S V D H Cycles Cycles
AND dst, src
dst ← dst AND src
r
r
52
–**0–– 2
3
r
Ir
53
2
4
R
R
54
3
3
R
IR
55
3
4
R
IM
56
3
3
IR
IM
57
3
4
ANDX dst, src
dst ← dst AND src
ER ER
58
–**0–– 4
3
ER IM
59
4
3
ATM
Block all interrupt and
DMA requests during
execution of the next 3
instructions
2F
––––– – 1
2
BCLR bit, dst
dst[bit] ← 0
r
E2
–**0–– 2
2
BIT p, bit, dst
dst[bit] ← p
r
E2
–**0–– 2
2
BRK
Debugger Break
00
––––– – 1
1
BSET bit, dst
dst[bit] ← 1
r
E2
–**0–– 2
2
BSWAP dst
dst[7:0] ← dst[0:7]
R
D5
X**0–– 2
2
BTJ p, bit, src, dst if src[bit] = p
PC ← PC + X
r
F6
––––– – 3
3
Ir
F7
3
4
BTJNZ bit, src, dst if src[bit] = 1
PC ← PC + X
r
F6
––––– – 3
3
Ir
F7
3
4
BTJZ bit, src, dst if src[bit] = 0
PC ← PC + X
r
F6
––––– – 3
3
Ir
F7
3
4
CALL dst
SP ← SP -2
@SP ← PC
PC ← dst
IRR
D4
––––– – 2
6
DA
D6
3
3
CCF
C ← ~C
EF
* – – – – –- 1
2
CLR dst
dst ← 00H
R
B0
––––– – 2
2
IR
B1
2
3
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024705-0405
PRELIMINARY
eZ8 CPU Instruction Set