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Z8F082ASH020SC Datasheet, PDF (29/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals
Z8 Encore! XP® F08xA Series
Product Specification
11
Table 3. Signal Descriptions (Continued)
Signal Mnemonic
I/O Description
VSS
I Digital Ground.
AVSS
I Analog Ground.
Note: The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by
PB6 and PB7 on 28-pin packages without ADC.
Pin Characteristics
Table 4 provides detailed information about the characteristics for each pin available on
the Z8 Encore! XP® F08xA Series 20- and 28-pin devices. Data in Table 4 is sorted alpha-
betically by the pin symbol mnemonic.
Table 4. Pin Characteristics (20- and 28-pin Devices)
Active Low
Internal Pull- Schmitt
Symbol
Reset
or
Tristate
up
Trigger
Mnemonic Direction Direction Active High Output or Pull-down Input
Open Drain
Output
5V
Tolerance
AVDD
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AVSS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NA
DBG
I/O
I
N/A
Yes
No
Yes
Yes
Yes
PA[7:0]
I/O
I
N/A
Yes Programmable Yes
Yes,
PA[7:2]
Pull-up
Programmable only
PB[7:0]
I/O
I
N/A
Yes Programmable Yes
Yes,
PB[7:6]
Pull-up
Programmable only
PC[7:0]
I/O
I
N/A
Yes Programmable Yes
Yes,
PC[7:3]
Pull-up
Programmable only
RESET/
PD0
I/O
I/O
Low (in Yes (PD0 programmable Yes programmable Yes
(defaults to Reset mode) only)
for PD0;
for PD0; always
RESET)
always on for
on for RESET
RESET
VDD
N/A
N/A
N/A
N/A
N/A
N/A
VSS
N/A
N/A
N/A
N/A
N/A
N/A
Note: PB6 and PB7 are available only in those devices without ADC.
PS024705-0405
PRELIMINARY
Pin Description