Z8F082ASH020SC Datasheet, PDF (35/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
17
Table 7. Register File Address Map (Continued)
Address (Hex)
FC2
FC3
FC4
FC5
FC6
FC7
FC8
FC9–FCC
FCD
FCE
FCF
Register Description
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
Interrupt Edge Select
Shared Interrupt Select
Interrupt Control
Mnemonic
IRQ0ENL
IRQ1
IRQ1ENH
IRQ1ENL
IRQ2
IRQ2ENH
IRQ2ENL
—
IRQES
IRQSS
IRQCTL
Reset (Hex)
00
00
00
00
00
00
00
XX
00
00
00
GPIO Port A
FD0
FD1
FD2
FD3
Port A Address
Port A Control
Port A Input Data
Port A Output Data
PAADDR
00
PACTL
00
PAIN
XX
PAOUT
00
GPIO Port B
FD4
FD5
FD6
FD7
Port B Address
Port B Control
Port B Input Data
Port B Output Data
PBADDR
00
PBCTL
00
PBIN
XX
PBOUT
00
GPIO Port C
FD8
FD9
FDA
FDB
Port C Address
Port C Control
Port C Input Data
Port C Output Data
PCADDR
00
PCCTL
00
PCIN
XX
PCOUT
00
GPIO Port D
FDC
FDD
FDE
FDF
FE0–FEF
Port D Address
Port D Control
Reserved
Port D Output Data
Reserved
PDADDR
00
PDCTL
00
—
XX
PDOUT
00
—
XX
Watch-Dog Timer (WDT)
XX=Undefined
Page #
53
52
54
55
52
55
56
57
57
57
37
38
39
39
37
38
39
39
37
38
39
39
37
38
39
PS024705-0405
PRELIMINARY
Register Map