Z8F082ASH020SC Datasheet, PDF (196/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
178
Table 115. Rotate and Shift Instructions
Mnemonic
SRL
SWAP
Operands
dst
dst
Instruction
Shift Right Logical
Swap Nibbles
eZ8 CPU Instruction Summary
Table 116 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 116. eZ8 CPU Instruction Summary
Assembly
Mnemonic
ADC dst, src
ADCX dst, src
ADD dst, src
ADDX dst, src
Flags Notation:
Symbolic Operation
Address Mode _Opcode(s)
Flags
Fetch Instr.
dst src
(Hex) C Z S V D H Cycles Cycles
dst ← dst + src + C
r
r
12
****0* 2
3
r
Ir
13
2
4
R
R
14
3
3
R
IR
15
3
4
R
IM
16
3
3
IR
IM
17
3
4
dst ← dst + src + C
ER ER
18
****0* 4
3
ER IM
19
4
3
dst ← dst + src
r
r
02
****0* 2
3
r
Ir
03
2
4
R
R
04
3
3
R
IR
05
3
4
R
IM
06
3
3
IR
IM
07
3
4
dst ← dst + src
ER ER
08
****0* 4
3
ER IM
09
4
3
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024705-0405
PRELIMINARY
eZ8 CPU Instruction Set