Z8F082ASH020SC Datasheet, PDF (33/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
15
Register Map
Table 7 provides the address map for the Register File of the Z8 Encore! XP^® F08xA
Series devices. Not all devices and package styles in the Z8 Encore! XP^® F08xA Series
support the ADC, or all of the GPIO Ports. Consider registers for unimplemented periph-
erals as Reserved.
Table 7. Register File Address Map
Address (Hex) Register Description
Mnemonic
General Purpose RAM
Z8F082A/Z8F081A Devices
000–3FF
General-Purpose Register File RAM
—
400–EFF
Reserved
—
Timer 0
F00
F01
F02
F03
F04
F05
F06
F07
Timer 1
F08
F09
F0A
F0B
F0C
F0D
F0E
F0F
F10–F3F
Timer 0 High Byte
Timer 0 Low Byte
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Timer 0 Control 0
Timer 0 Control 1
Timer 1 High Byte
Timer 1 Low Byte
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Timer 1 Control 0
Timer 1 Control 1
Reserved
T0H
T0L
T0RH
T0RL
T0PWMH
T0PWML
T0CTL0
T0CTL1
T1H
T1L
T1RH
T1RL
T1PWMH
T1PWML
T1CTL0
T1CTL1
—
UART 0
F40
XX=Undefined
UART0 Transmit Data
UART0 Receive Data
U0TXD
U0RXD
Reset (Hex)
XX
XX
00
01
FF
FF
00
00
00
00
00
01
FF
FF
00
00
00
00
XX
XX
XX
Page #
72
72
73
73
73
74
74
75
72
72
73
73
73
74
74
72
95
96
PS024705-0405
PRELIMINARY
Register Map