|
Z8F082ASH020SC Datasheet, PDF (115/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals | |||
|
◁ |
Z8 Encore! XP® F08xA Seriess
Product Specification
97
0 = No parity error has occurred.
1 = A parity error has occurred.
OEâOverrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data register has not been read. If the RDA bit is reset to
0, reading the UART Receive Data register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FEâFraming Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKDâBreak Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop
bit(s) are all 0s this bit is set to 1. Reading the UART Receive Data register clears this bit.
0 = No break occurred.
1 = A break occurred.
TDREâTransmitter Data Register Empty
This bit indicates that the UART Transmit Data register is empty and ready for additional
data. Writing to the UART Transmit Data register resets this bit.
0 = Do not write to the UART Transmit Data register.
1 = The UART Transmit Data register is ready to receive an additional byte to be transmit-
ted.
TXEâTransmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is fin-
ished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTSâCTS signal
When this bit is read it returns the level of the CTS signal. This signal is active Low.
UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 63. UART Status 1 Register (U0STAT1)
BITS
7
6
5
4
3
2
FIELD
Reserved
RESET
0
0
0
0
0
0
1
NEWFRM
0
0
MPRX
0
PS024705-0405
PRELIMINARY
UART
|
▷ |