Z8F082ASH020SC Datasheet, PDF (41/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
23
VCC = 3.3V
V_POR
V_VBO
Program
Execution
Voltage
Brownout
VCC = 3.3V
Program
Execution
WDT Clock
System Clock
Internal RESET
signal
Note: Not to Scale
POR
counter delay
Figure 5.Voltage Brown-Out Reset Operation
The POR level is greater than the VBO level by the specified hysteresis value. This
ensures that the device undergoes a power on reset after recovering from a VBO condition.
Watch-Dog Timer Reset
If the device is in NORMAL or STOP mode, the Watch-Dog Timer can initiate a System
Reset at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the
unprogrammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it
configures the Watch-Dog Timer to cause an interrupt, not a System Reset, at time-out.
The WDT status bit in the WDT Control register is set to signify that the reset was initi-
ated by the Watch-Dog Timer.
External Reset Input
The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of 4 system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
clock and reset signals, the required reset duration may be as short as three clock periods
PS024705-0405
PRELIMINARY
Reset and STOP Mode Recovery