Z8F082ASH020SC Datasheet, PDF (66/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
48
Table 31. Trap and Interrupt Vectors in Order of Priority (Continued)
Program Memory
Priority Vector Address Interrupt or Trap Source
Lowest 0036H
Port C0, both input edges
0038H
Reserved
Architecture
Figure 7 illustrates the interrupt controller block diagram.
Port Interrupts
Internal Interrupts
High
Priority
Medium
Priority
Vector
Priority
Mux
IRQ Request
Low
Priority
Figure 7.Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
• Execution of an EI (Enable Interrupt) instruction
• Execution of an IRET (Return from Interrupt) instruction
PS024705-0405
PRELIMINARY
Interrupt Controller