Z8F082ASH020SC Datasheet, PDF (47/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
29
HALT Mode
Executing the eZ8 CPU’s HALT instruction places the device into HALT mode. In HALT
mode, the operating characteristics are:
• Primary oscillator is enabled and continues to operate
• System clock is enabled and continues to operate
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• Watch-Dog Timer’s internal RC oscillator continues to operate
• If enabled, the Watch-Dog Timer continues to operate
• All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
• Interrupt
• Watch-Dog Timer time-out (interrupt or reset)
• Power-on reset
• Voltage-brown out reset
• External RESET pin assertion
To minimize current in HALT mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (V_CC or GND).
Peripheral-Level Power Control
In addition to the STOP and Halt modes, it is possible to disable each peripheral on each
of the Z8 Encore! XP^® F08xA Series devices. Disabling a given peripheral minimizes its
power consumption.
Power Control Register Definitions
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
The default state of the transimpedance amplifier is OFF. To use the transimpedance
amplifier, clear the TRAM bit, turning it ON. Clearing this bit might interfere with normal
PS024705-0405
PRELIMINARY
Low-Power Modes