Z8F082ASH020SC Datasheet, PDF (44/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
26
STOP Mode Recovery Using the External RESET Pin
When the Z8 Encore! XP^® F08xA Series device is in STOP Mode and the external
RESET pin is driven Low, a system reset occurs. Because of a glitch filter operating on the
RESET pin, the Low pulse must be greater than the minimum width specified, or it is
ignored. See “Electrical Characteristics” on page 191 for details.
Reset Register Definitions
Reset Status Register
The Reset Status (RSTSTAT) register is a read-only register that indicates the source of
the most recent Reset event, indicates a STOP Mode Recovery event, and indicates a
Watch-Dog Timer time-out. Reading this register resets the upper four bits to 0.
This register shares its address with the Watch-Dog Timer control register, which is write-
only (Table 11).
Table 11. Reset Status Register (RSTSTAT)
BITS
7
6
5
4
3
2
1
0
FIELD
POR
STOP
WDT
EXT
Reserved
RESET
See descriptions below
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
ADDR
FF0H
Reset or STOP Mode Recovery Event
Power-On Reset
Reset using RESET pin assertion
Reset using Watch-Dog Timer time-out
Reset using the On-Chip Debugger (OCTCTL[1] set to 1)
Reset from STOP Mode using DBG Pin driven Low
STOP Mode Recovery using GPIO pin transition
STOP Mode Recovery using Watch-Dog Timer time-out
POR
1
0
0
1
1
0
0
STOP
0
0
0
0
0
1
1
WDT
0
0
1
0
0
0
1
EXT
0
1
0
0
0
0
0
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-
out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—STOP Mode Recovery Indicator
If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both
PS024705-0405
PRELIMINARY
Reset and STOP Mode Recovery