Z8F082ASH020SC Datasheet, PDF (55/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
37
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 15 lists these Port registers. Use the Port A–D Address and Control registers
together to provide access to sub-registers for Port configuration and control.
Table 15. GPIO Port Registers and Sub-Registers
Port Register Mnemonic
PxADDR
PxCTL
PxIN
PxOUT
Port Sub-Register Mnemonic
PxDD
PxAF
PxOC
PxHDE
PxSMRE
PxPUE
PxAFS1
PxAFS2
Port Register Name
Port A–D Address Register
(Selects sub-registers)
Port A–D Control Register
(Provides access to sub-registers)
Port A–D Input Data Register
Port A–D Output Data Register
Port Register Name
Data Direction
Alternate Function
Output Control (Open-Drain)
High Drive Enable
STOP Mode Recovery Source Enable
Pull-up Enable
Alternate Function Set 1
Alternate Function Set 2
Port A–D Address Registers
The Port A–D Address registers select the GPIO Port functionality accessible through the
Port A–D Control registers. The Port A–D Address and Control registers combine to pro-
vide access to all GPIO Port controls (Table 16).
Table 16. Port A–D GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
2
1
0
FIELD
PADDR[7:0]
RESET
00H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FD0H, FD4H, FD8H, FDCH
PS024705-0405
PRELIMINARY
General-Purpose I/O