Z51F3220FNX Datasheet, PDF (9/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
Figure 11.52 12-bit ADC Block Diagram ................................................................................................. 179
Figure 11.53 A/D Analog Input Pin with Capacitor .................................................................................. 179
Figure 11.54 A/D Power (AVREF) Pin with Capacitor ............................................................................ 179
Figure 11.55 ADC Operation for Align Bit................................................................................................ 180
Figure 11.56 A/D Converter Operation Flow ........................................................................................... 182
Figure 11.57 USI0 UART Block Diagram ................................................................................................ 187
Figure 11.58 Clock Generation Block Diagram (USI0) ........................................................................... 188
Figure 11.59 Synchronous Mode SCK0 Timing (USI0) .......................................................................... 189
Figure 11.60 Frame Format (USI0) ......................................................................................................... 190
Figure 11.61 Asynchronous Start Bit Sampling (USI0) ........................................................................... 194
Figure 11.62 Asynchronous Sampling of Data and Parity Bit (USI0) ..................................................... 194
Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0) ..................................................... 195
Figure 11.64 USI0 SPI Clock Formats when CPHA0=0 ......................................................................... 197
Figure 11.65 USI0 SPI Clock Formats when CPHA0=1 ......................................................................... 198
Figure 11.66 USI0 SPI Block Diagram .................................................................................................... 199
Figure 11.67 Bit Transfer on the I2C-Bus (USI0) .................................................................................... 200
Figure 11.68 START and STOP Condition (USI0) .................................................................................. 201
Figure 11.69 Data Transfer on the I2C-Bus (USI0)................................................................................. 201
Figure 11.70 Acknowledge on the I2C-Bus (USI0) ................................................................................. 202
Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0).............................................. 203
Figure 11.72 Arbitration Procedure of Two Masters (USI0) .................................................................... 203
Figure 11.73 Formats and States in the Master Transmitter Mode (USI0)............................................. 205
Figure 11.74 Formats and States in the Master Receiver Mode (USI0) ................................................. 207
Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)............................................... 209
Figure 11.76 Formats and States in the Slave Receiver Mode (USI0) ................................................... 211
Figure 11.77 USI0 I2C Block Diagram .................................................................................................... 212
Figure 11.78 USI1 UART Block Diagram ................................................................................................ 224
Figure 11.79 Clock Generation Block Diagram (USI1) ........................................................................... 225
Figure 11.80 Synchronous Mode SCK1 Timing (USI1) .......................................................................... 226
Figure 11.81 Frame Format (USI1) ......................................................................................................... 227
Figure 11.82 Asynchronous Start Bit Sampling (USI1) ........................................................................... 231
Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1) ..................................................... 231
Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1) ..................................................... 232
Figure 11.85 USI1 SPI Clock Formats when CPHA1=0 ......................................................................... 234
Figure 11.86 USI1 SPI Clock Formats when CPHA1=1 ......................................................................... 235
Figure 11.87 USI1 SPI Block Diagram .................................................................................................... 236
Figure 11.88 Bit Transfer on the I2C-Bus (USI1) .................................................................................... 237
Figure 11.89 START and STOP Condition (USI1) .................................................................................. 238
Figure 11.90 Data Transfer on the I2C-Bus (USI1)................................................................................. 238
Figure 11.91 Acknowledge on the I2C-Bus (USI1) ................................................................................. 239
Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1).............................................. 240
Figure 11.93 Arbitration Procedure of Two Masters (USI1) .................................................................... 240
Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)............................................. 242
Figure 11.95 Formats and States in the Master Receiver Mode (USI1) ................................................. 244
Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)............................................... 246
Figure 11.97 Formats and States in the Slave Receiver Mode (USI1) ................................................... 248
Figure 11.98 USI1 I2C Block Diagram .................................................................................................... 249
Figure 11.99 LCD Circuit Block Diagram................................................................................................. 261
Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)...................................................................... 262
PS029902-0212
PRELIMINARY
6