Z51F3220FNX Datasheet, PDF (231/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.13.9.3 USI1 UART Parity Generator
The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled
(USI1PM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the
frame to be sent.
11.13.9.4 USI1 UART Disabling Transmitter
Disabling the transmitter by clearing the TXE1 bit will not become effective until ongoing transmission is
completed. When the Transmitter is disabled, the TXD1 pin can be used as a normal general purpose I/O (GPIO).
11.13.10 USI1 UART Receiver
The UART receiver is enabled by setting the RXE1 bit in the USI1CR2 register. When the receiver is enabled,
the RXD1 pin should be set to RXD1 function for the serial input pin of UART by P1FSR[1:0]. The baud-rate,
mode of operation and frame format must be set before serial reception. In synchronous or SPI operation mode
the SCK1 pin is used as transfer clock, so it should be selected to do SCK1 function by P2FSR[3:2]. In SPI
operation mode the SS1 input pin in slave mode or can be configured as SS1 output pin in master mode. This
can be done by setting USI1SSEN bit in USI1CR3 register.
11.13.10.1 USI1 UART Receiving Rx data
When UART is in synchronous or asynchronous operation mode, the receiver starts data reception when it
detects a valid start bit (LOW) on RXD1 pin. Each bit after start bit is sampled at pre-defined baud-rate
(asynchronous) or sampling edge of SCK1 (synchronous), and shifted into the receive shift register until the first
stop bit of a frame is received. Even if there’s 2^nd stop bit in the frame, the 2^nd stop bit is ignored by the receiver.
That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and
contents of the shift register are to be moved into the receive buffer. The receive buffer is read by reading the
USI1DR register.
If 9-bit characters are used (USI1S[2:0] = “111”), the ninth bit is stored in the USI1RX8 bit position in the
USI1CR3 register. The 9^th bit must be read from the USI1RX8 bit before reading the low 8 bits from the USI1DR
register. Likewise, the error flags FE1, DOR1, PE1 must be read before reading the data from USI1DR register.
It’s because the error flags are stored in the same FIFO position of the receive buffer.
PS029902-0212
PRELIMINARY
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