Z51F3220FNX Datasheet, PDF (254/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
USI1SCLR (USI1 SCL Low Period Register: For I2C mode) : F6H
7
6
5
4
3
USI1SCLR7 USI1SCLR6 USI1SCLR5 USI1SCLR 4 USI1SCLR 3
R/W
R/W
R/W
R/W
R/W
2
USI1SCLR 2
R/W
1
0
USI1SCLR 1 USI1SCLR 0
R/W
R/W
Initial value : 00H
USI1SCLR[7:0]
This register defines the high period of SCL1 when it operates in
I2C master mode.
The base clock is SCLK, the system clock, and the period is
calculated by the formula: tSCLK X (4 X USI1SCLR +2) where
tSCLK is the period of SCLK.
USI1SAR (USI1 Slave Address Register: For I2C mode) : EDH
7
6
5
4
3
USI1SLA6 USI1SLA5 USI1SLA4 USI1SLA3 USI1SLA2
R/W
R/W
R/W
R/W
R/W
2
USI1SLA1
R/W
1
0
USI1SLA0 USI1GCE
R/W
R/W
Initial value : 00H
USI1SLA[6:0]
UPM[1:0]
These bits configure the slave address of I2C when it operaties in
I2C slave mode.
This bit decides whether I2C allows general call address or not in
I2C slave mode.
0
Ignore general call address
1
Allow general call address
PS029902-0212
PRELIMINARY
252