Z51F3220FNX Datasheet, PDF (230/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.13.9 USI1 UART Transmitter
The UART transmitter is enabled by setting the TXE1 bit in USI1CR2 register. When the Transmitter is enabled,
the TXD1 pin should be set to TXD1 function for the serial output pin of UART by the P2FSR[1:0]. The baud-rate,
operation mode and frame format must be setup once before doing any transmission. In synchronous operation
mode, the SCK1 pin is used as transmission clock, so it should be selected to do SCK1 function by P2FSR[3:2] .
11.13.9.1 USI1 UART Sending Tx data
A data transmission is initiated by loading the transmit buffer (USI1DR register I/O location) with the data to be
transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to
send a new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last
stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one
complete frame according to the settings of control registers. If the 9-bit characters are used in asynchronous or
synchronous operation mode, the ninth bit must be written to the USI1TX8 bit in USI1CR3 register before it is
loaded to the transmit buffer (USI1DR register).
11.13.9.2 USI1 UART Transmitter flag and interrupt
The UART transmitter has 2 flags which indicate its state. One is UART data register empty flag (DRE1) and the
other is transmit complete flag (TXC1). Both flags can be interrupt sources.
DRE1 flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit
buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved
into the shift register. And also this flag can be cleared by writing ‘0’ to this bit position. Writing ‘1’ to this bit
position is prevented.
When the data register empty interrupt enable (DRIE1) bit in USI1CR2 register is set and the global interrupt is
enabled, USI1ST1 status register empty interrupt is generated while DRE1 flag is set.
The transmit complete (TXC1) flag bit is set when the entire frame in the transmit shift register has been shifted
out and there is no more data in the transmit buffer. The TXC1 flag is automatically cleared when the transmit
complete interrupt service routine is executed, or it can be cleared by writing ‘0’ to TXC1 bit in USI1ST1 register.
When the transmit complete interrupt enable (TXCIE1) bit in USI1CR2 register is set and the global interrupt is
enabled, UART transmit complete interrupt is generated while TXC1 flag is set.
PS029902-0212
PRELIMINARY
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