Z51F3220FNX Datasheet, PDF (176/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.10.3 Data Transmit / Receive Operation
User can use SPI 2 for serial data communication by following step
1. Select SPI 2 operation mode(master/slave, polarity, phase) by control register SPICR.
2. When the SPI 2 is configured as a Master, it selects a Slave by SS2 signal (active low).
When the SPI 2 is configured as a Slave, it is selected by SS2 signal incoming from Master
3. When the user writes a byte to the data register SPIDR, SPI 2 will start an operation.
4. In this time, if the SPI 2 is configured as a Master, serial clock will come out of SCK2 pin. And Master shifts the
eight bits into the Slave (transmit), Slave shifts the eight bits into the Master at the same time (receive). If the
SPI 2 is configured as a Slave, serial clock will come into SCK2 pin. And Slave shifts the eight bits into the
Master (transmit), Master shifts the eight bits into the Slave at the same time (receive).
5. When transmit/receive is done, SPIIFR bit will be set. If the SPI 2 interrupt is enabled, an interrupt is requested.
And SPIIFR bit is cleared by hardware when executing the corresponding interrupt. If SPI 2 interrupt is disable,
SPIIFR bit is cleared when user read the status register SPISR, and then access (read/write) the data register
SPIDR.
11.10.4 SS2 pin function
1. When the SPI 2 is configured as a Slave, the SS2 pin is always input. If LOW signal come into SS2 pin, the
SPI 2 logic is active. And if ‘HIGH’ signal come into SS2 pin, the SPI 2 logic is stop. In this time, SPI 2 logic will
be reset, and invalidated any received data.
2. When the SPI 2 is configured as a Master, the user can select the direction of the SS2 pin by port direction
register (P17IO). If the SS2 pin is configured as an output, user can use general P17IO output mode. If the
SS2 pin is configured as an input, ‘HIGH’ signal must come into SS2 pin to guarantee Master operation. If
‘LOW’ signal come into SS2 pin, the SPI 2 logic interprets this as another master selecting the SPI 2 as a slave
and starting to send data to it. To avoid bus contention, MSB bit of SPICR will be cleared and the SPI 2
becomes a Slave and then, SPIIFR bit of SPISR will be set, and if the SPI 2 interrupt is enabled, an interrupt is
requested.
NOTES)
- When the SS2 pin is configured as an output at Master mode, SS2 pin’s output value is defined by user’s
software (P17IO). Before SPICR setting, the direction of SS2 pin must be defined
- If you don’t need to use SS2 pin, clear the SSENA bit of SPISR. So, you can use disabled pin by P17IO freely.
In this case, SS2 signal is driven by ‘HIGH’ or ‘LOW’ internally. In other words, master is ‘HIGH’, salve is ‘LOW’
- When SS2 pin is configured as input, if ‘HIGH’ signal come into SS2 pin, SS_HIGH flag bit will be set. And you
can clear it by writing ‘0’.
PS029902-0212
PRELIMINARY
173