Z51F3220FNX Datasheet, PDF (249/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.13.20.4 USI1 I2C Slave Receiver
To operate I2C in slave receiver, follow the recommended steps below.
8. If the main operating clock (SCLK) of the system is slower than that of SCL1, load value 0x00 into
USI1SDHR to make SDA1 change within one system clock period from the falling edge of SCL1. Note
that the hold time of SDA1 is calculated by SDAH x period of SCLK where SDAH is multiple of number
of SCLK coming from USI1SDHR. When the hold time of SDA1 is longer than the period of SCLK, I2C
(slave) cannot transmit serial data properly.
9. Enable I2C by setting USI1MS[1:0] bits in USI1CR1, IIC1IE bit in USI1CR4 and USI1EN bit in USI1CR2.
This provides main clock to the peripheral.
10. When a START condition is detected, I2C receives one byte of data and compares it with USI1SLA[6:0]
bits in USI1SAR. If the GCALL1 bit in USI1SAR is enabled, I2C1 compares the received data with value
0x00, the general call address.
11. If the received address does not equal to SLA1 bits in USI1SAR, I2C enters idle state ie, waits for
another START condition. Else if the address equals to SLA1 bits and the ACK1EN bit is enabled, I2C
generates SSEL1 interrupt and the SCL1 line is held LOW. Note that even if the address equals to
SLA1 bits, when the ACK1EN bit is disabled, I2C enters idle state. When SSEL1 interrupt occurs and
I2C is ready to receive data, write arbitrary value to USI1ST2 to release SCL1 line.
12. 1-Byte of data is being received.
13. In this step, I2C generates TEND1 interrupt and holds the SCL1 line LOW regardless of the reception of
ACK signal from master. Slave can select one of the following cases.
1) No ACK signal is detected (ACK1EN=0) and I2C waits STOP or repeated START condition.
2) ACK signal is detected (ACK1EN=1) and I2C can continue to receive data from master.
After doing one of the actions above, write arbitrary value to USI1ST2 to release SCL1 line. In case of 1)
move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a repeated
START condition can be detected. For that case, move step 4.
14. This is the final step for slave receiver function of I2C, handling STOP interrupt. The STOPC1 bit
indicates that data transfer between master and slave is over. To clear USI1ST2, write any value to
USI1ST2. After this, I2C enters idle state.
PS029902-0212
PRELIMINARY
247