Z51F3220FNX Datasheet, PDF (134/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.7.2 16-Bit Timer/Counter Mode
The 16-bit timer/counter mode is selected by control register as shown in Figure 11.22.
The 16-bit timer have counter and data register. The counter register is increased by internal or timer 1 A match
clock input. Timer 2 can use the input clock with one of 1, 2, 4, 8, 32, 128, 512 and T1 A Match prescaler division
rates (T2CK[2:0]). When the values of T2CNTH/T2CNTL and T2ADRH/T2ADRL are identical in timer 2, a match
signal is generated and the interrupt of Timer 2 occurs. The T2CNTH/T2CNTL values are automatically cleared
by match signal. It can be also cleared by software (T2CC).
T2CRH T2 EN
–
T2MS1 T2MS0
–
–
–
T2CC
ADDRESS:C3H
INITIAL VALUE: 0000_0000 B
1
–
0
0
–
–
–
X
T2 CRL
T2CK2 T2 CK1 T2CK0
X
X
X
T2IFR
X
–
T2POL
–
X
– T2CNTR ^ADDRESS:C2H
INITIAL VALUE: 0000_0000 B
–
X
16 -bit A Data Register
T2ADRH/T2ADRL
T2CK[2:0 ]
3
T1 A Match
P
fx/1
r
fx/2
e
fx/4
M
fx
s
c
fx/8
U
X
a fx/32
l _fx/128
e
r ^fx/512
T2EN
Reload
Buffer Register A
A Match
Comparator
16 -bit Counter _R
T2 CNTH/T2CNTL
Clear
A Match
T2CC
T2EN
INT_ ACK
Clear
T2IFR
To interrupt
block
A Match
T2CC
T2EN
Pulse
Generator
T2 O
2
T2MS[1:0] T2POL
Figure 11.22 16-Bit Timer/Counter Mode for Timer 2
PS029902-0212
PRELIMINARY
131