Z51F3220FNX Datasheet, PDF (110/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.3.6 Register Description for Watch Dog Timer
WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH
7
6
5
4
3
2
WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2
R
R
R
R
R
R
WDTCNT[7:0] WDT Counter
1
0
WDTCNT 1 WDTCNT 0
R
R
Initial value : 00H
WDTDR (Watch Dog Timer Data Register: Write Case) : 8EH
7
6
5
4
3
WDTDR7 WDTDR 6 WDTDR 5 WDTDR 4 WDTDR 3
W
W
W
W
W
2
WDTDR 2
W
1
0
WDTDR 1 WDTDR 0
W
W
Initial value : FFH
WDTDR[7:0]
Set a period
WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1)
NOTE) Do not write “0” in the WDTDR register.
WDTCR (Watch Dog Timer Control Register) : 8DH
7
6
5
4
3
WDTEN WDTRSON WDTCL
–
–
R/W
R/W
R/W
–
–
2
1
0
–
WDTCK
WDTIFR
–
R/W
R/W
Initial value : 00H
WDTEN
WDTRSON
WDTCL
WDTCK
WDTIFR
Control WDT Operation
0
Disable
1
Enable
Control WDT RESET Operation
0
Free Running 8-bit timer
1
Watch Dog Timer RESET ON
Clear WDT Counter
0
Free Run
1
Clear WDT Counter (auto clear after 1 Cycle)
Control WDT Clock Selection Bit
0
BIT overflow for WDT clock (WDTRC disable)
1
WDTRC for WDT xlock (WDTRC enable)
When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write
‘0’ to this bit or auto clear by INT_ACK signal.
0
WDT Interrupt no generation
1
WDT Interrupt generation
PS029902-0212
PRELIMINARY
107