Z51F3220FNX Datasheet, PDF (214/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.12.21 USI0 I2C Block Diagram
SDA0
N-ch
VSS
SCL0
N-ch
VSS
RXACK0, GCALL 0,
TEND0, STOPD0,
SSEL 0, MLOST0,
BUSY0, TMODE0
SDA0 In/Out
Controller
SCL0 Out
Controller
IIC0IFR
Interrupt
Generator
IIC0IE
To interrupt
block
Slave Address Register
USI0SAR
General Call And
Address Detector
Receive Shift Register
( RXSR)
ACK Signal
Generator
ACK0EN
USI0DR, ( Rx)
USI0GCE
I
N
T
E
R
N
A
L
STOP /START
STOPC0
B
Condition Generator
STARTC0
U
S
Transmit Shift Register
(TXSR)
USI0DR, (Tx)
L
I
SDA Hold Time Register
N
USI0SDHR
E
Time Generator
And
Time Controller
SCL High Period Register
USI0SCHR
SCL Low Period Register
USI0SCLR
SCLK
(fx: System clock)
NOTE) When the USI0 block is an I2C mode and the corresponding port is an sub-function for SCL0/SDA0
pin, the SCL0/SDA0 pins are automatically set to the N-channel open-drain outputs and the input latch is
read in the case of reading the pins. The corresponding pull-up resistor is determined by the control
register.
Figure 11.77 USI0 I2C Block Diagram
PS029902-0212
PRELIMINARY
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