Z51F3220FNX Datasheet, PDF (246/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
18. This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit
indicates that data transfer between master and slave is over. To clear USI1ST2, write any value to
USI1ST2. After this, I2C enters idle state.
The processes described above for master receiver operation of I2C can be depicted as the following figure.
Master
Transmitter
SLA+W
S or Sr
SLA+R
ACK ^N
0x85 ^Y
0x84
0x20
STOP
P
0x0C
LOST
DATA
Rs
0x44
ACK ^N
0x45 _Y
0x44
0x0C
LOST LOST&
0x0D 0x1D 0x1F ^{Slave Receiver (0x1D)}
or Transmitter (0x1F)
Sr
0x20
STOP
P
LOST ^{Other master continues}
0xxx
From master to slave /
Master command or Data Write
From slave to master
Value of Status Register
ACK
ACK
Interrupt, SCL1 line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
Figure 11.95 Formats and States in the Master Receiver Mode (USI1)
PS029902-0212
PRELIMINARY
244