Z51F3220FNX Datasheet, PDF (193/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.12.9 USI0 UART Transmitter
The UART transmitter is enabled by setting the TXE0 bit in USI0CR2 register. When the Transmitter is enabled,
the TXD0 pin should be set to TXD0 function for the serial output pin of UART by the P4FSR[3:2]. The baud-rate,
operation mode and frame format must be setup once before doing any transmission. In synchronous operation
mode, the SCK0 pin is used as transmission clock, so it should be selected to do SCK0 function by P4FSR[5:4] .
11.12.9.1 USI0 UART Sending Tx data
A data transmission is initiated by loading the transmit buffer (USI0DR register I/O location) with the data to be
transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to
send a new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last
stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one
complete frame according to the settings of control registers. If the 9-bit characters are used in asynchronous or
synchronous operation mode, the ninth bit must be written to the USI0TX8 bit in USI0CR3 register before it is
loaded to the transmit buffer (USI0DR register).
11.12.9.2 USI0 UART Transmitter flag and interrupt
The UART transmitter has 2 flags which indicate its state. One is UART data register empty flag (DRE0) and the
other is transmit complete flag (TXC0). Both flags can be interrupt sources.
DRE0 flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit
buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved
into the shift register. And also this flag can be cleared by writing ‘0’ to this bit position. Writing ‘1’ to this bit
position is prevented.
When the data register empty interrupt enable (DRIE0) bit in USI0CR2 register is set and the global interrupt is
enabled, USI0ST1 status register empty interrupt is generated while DRE0 flag is set.
The transmit complete (TXC0) flag bit is set when the entire frame in the transmit shift register has been shifted
out and there is no more data in the transmit buffer. The TXC0 flag is automatically cleared when the transmit
complete interrupt service routine is executed, or it can be cleared by writing ‘0’ to TXC0 bit in USI0ST1 register.
When the transmit complete interrupt enable (TXCIE0) bit in USI0CR2 register is set and the global interrupt is
enabled, UART transmit complete interrupt is generated while TXC0 flag is set.
PS029902-0212
PRELIMINARY
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