Z51F3220FNX Datasheet, PDF (280/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
13.4 RESET Noise Canceller
The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation
value of about 2us (@VDD=5V) to the low input of system reset.
t < TRNC
t < TRNC
A
t > TRNC
t > TRNC
t > TRNC
A’
Figure 13.2 Reset noise canceller timer diagram
13.5 Power on RESET
When rising device power, the POR (Power On Reset) has a function to reset the device. If POR is used, it
executes the device RESET function instead of the RESET IC or the RESET circuits.
Fast VDD Rise Time
VDD
nPOR
(Internal Signal)
Internal RESETB
BIT Starts
BIT Overflows
Oscillation
Figure 13.3 Fast VDD Rising Time
Slow VDD Rise Time, min. 0.15V/mS
VDD
nPOR
(Internal Signal)
Internal RESETB
VPOR=1.4V (Typ)
BIT Starts
BIT Overflows
Oscillation
Figure 13.4 Internal RESET Release Timing On Power-Up
PS029902-0212
PRELIMINARY
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