Z51F3220FNX Datasheet, PDF (257/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
USI1CR3 (USI1 Control Register 3: For UART, SPI, and I2C mode) : EBH
7
6
5
4
3
2
MASTER1 LOOPS1
DISSCK1 USI1SSEN
FXCH1
USI1SB
R/W
R/W
R/W
R/W
R/W
R/W
1
0
USI1TX8
USI1RX8
R/W
R
Initial value : 00H
MASTER1
LOOPS1
DISSCK1
USI1SSEN
FXCH1
USI1SB
USI1TX8
USI1RX8
Selects master or slave in SPI and synchronous mode operation and
controls the direction of SCK1 pin
0
Slave mode operation (External clock for SCK1).
1
Master mode operation(Internal clock for SCK1).
Controls the loop back mode of USI1 for test mode (only UART and SPI
mode)
0
Normal operation
1
Loop Back mode
In synchronous mode of operation, selects the waveform of SCK1 output
0
ACK is free-running while UART is enabled in synchronous
master mode
1
ACK is active while any frame is on transferring
This bit controls the SS1 pin operation (only SPI mode)
0
Disable
1
Enable (The SS1 pin should be a normal input)
SPI port function exchange control bit (only SPI mode)
0
No effect
1
Exchange MOSI1 and MISO1 function
Selects the length of stop bit in asynchronous or synchronous mode of
operation.
0
1 Stop Bit
1
2 Stop Bit
The ninth bit of data frame in asynchronous or synchronous mode of
operation. Write this bit first before loading the USI1DR register
0
MSB (9^th bit) to be transmitted is ‘0’
1
MSB (9^th bit) to be transmitted is ‘1’
The ninth bit of data frame in asynchronous or synchronous mode of
operation. Read this bit first before reading the receive buffer (only UART
mode).
0
MSB (9^th bit) received is ‘0’
1
MSB (9^th bit) received is ‘1’
PS029902-0212
PRELIMINARY
255