Z51F3220FNX Datasheet, PDF (251/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.13.21 USI1 I2C Block Diagram
SDA1
N-ch
VSS
SCL1
N-ch
VSS
RXACK1, GCALL 1,
TEND1, STOPD1,
SSEL 1, MLOST1,
BUSY1, TMODE1
SDA1 In/Out
Controller
SCL1 Out
Controller
IIC1IFR
Interrupt
Generator
IIC1IE
To interrupt
block
Slave Address Register
USI1SAR
General Call And
Address Detector
Receive Shift Register
( RXSR)
ACK Signal
Generator
ACK1EN
USI1DR, ( Rx)
USI1GCE
I
N
T
E
R
N
A
L
STOP /START
STOPC1
B
Condition Generator
STARTC1
U
S
Transmit Shift Register
(TXSR)
USI1DR, (Tx)
L
I
SDA Hold Time Register
N
USI1SDHR
E
Time Generator
And
Time Controller
SCL High Period Register
USI1SCHR
SCL Low Period Register
USI1SCLR
SCLK
(fx: System clock)
NOTE) When the USI1 block is an I2C mode and the corresponding port is an sub-function for SCL1/SDA1 pin,
the SCL1/SDA1 pins are automatically set to the N-channel open-drain outputs and the input latch is read in
the case of reading the pins. The corresponding pull-up resistor is determined by the control register.
Figure 11.98 USI1 I2C Block Diagram
PS029902-0212
PRELIMINARY
249