Z51F3220FNX Datasheet, PDF (195/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.12.10.2 USI0 UART Receiver Flag and Interrupt
The UART receiver has one flag that indicates the receiver state.
The receive complete (RXC0) flag indicates whether there are unread data in the receive buffer. This flag is set
when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is
disabled (RXE0=0), the receiver buffer is flushed and the RXC0 flag is cleared.
When the receive complete interrupt enable (RXCIE0) bit in the USI0CR2 register is set and global interrupt is
enabled, the UART receiver complete interrupt is generated while RXC0 flag is set.
The UART receiver has three error flags which are frame error (FE0), data overrun (DOR0) and parity error
(PE0). These error flags can be read from the USI0ST1 register. As received data are stored in the 2-level
receive buffer, these error flags are also stored in the same position of receive buffer. So, before reading
received data from USI0DR register, read the USI0ST1 register first which contains error flags.
The frame error (FE0) flag indicates the state of the first stop bit. The FE0 flag is ‘0’ when the stop bit was
correctly detected as “1”, and the FE0 flag is “1” when the stop bit was incorrect, i.e. detected as “0”. This flag
can be used for detecting out-of-sync conditions between data frames.
The data overrun (DOR0) flag indicates data loss due to a receive buffer full condition. DOR0 occurs when the
receive buffer is full, and another new data is present in the receive shift register which are to be stored into the
receive buffer. After the DOR0 flag is set, all the incoming data are lost. To prevent data loss or clear this flag,
read the receive buffer.
The parity error (PE0) flag indicates that the frame in the receive buffer had a parity error when received. If
parity check function is not enabled (USI0PM1=0), the PE bit is always read “0”.
11.12.10.3 USI0 UART Parity Checker
If parity bit is enabled (USI0PM1=1), the Parity Checker calculates the parity of the data bits in incoming frame
and compares the result with the parity bit from the received serial frame.
11.12.10.4 USI0 UART Disabling Receiver
In contrast to transmitter, disabling the Receiver by clearing RXE0 bit makes the Receiver inactive immediately.
When the receiver is disabled, the receiver flushes the receive buffer, the remaining data in the buffer is all reset,
and the RXD0 pin can be used as a normal general purpose I/O (GPIO).
PS029902-0212
PRELIMINARY
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