Z51F3220FNX Datasheet, PDF (133/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.7 Timer 2
11.7.1.1 Overview
The 16-bit timer 2 consists of multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and
timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, T2CRL).
It has four operating modes:
- 16-bit timer/counter mode
- 16-bit capture mode
- 16-bit PPG output mode (one-shot mode)
- 16-bit PPG output mode (repeat mode)
The timer/counter 2 can be divided clock of the system clock selectd from prescaler output and T1 A Match
(timer 1 A match signal). The clock source is selected by clock selection logic which is controlled by the clock
selection bits (T2CK[2:0]).
- TIMER 2 clock source: fX/1, 2, 4, 8, 32, 128, 512 and T1 A Match
In the capture mode, by EINT12, the data is captured into input capture data register (T2BDRH/T2BDRL). In
timer/counter mode, whenever counter value is equal to T2ADRH/L, T2O port toggles. Also the timer 2 outputs
PWM wave form to PWM2O port in the PPG mode.
T2EN
1
1
1
1
Table 11-9 Timer 2 Operating Modes
P1FSRL[3:2]
11
00
11
11
T2MS[1:0]
00
01
10
11
T2CK[2:0]
XXX
XXX
XXX
XXX
Timer 2
16 Bit Timer/Counter Mode
16 Bit Capture Mode
16 Bit PPG Mode
(one-shot mode)
16 Bit PPG Mode
(repeat mode)
PS029902-0212
PRELIMINARY
130