Z51F3220FNX Datasheet, PDF (185/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.11.7 Register Description for ADC
ADCDRH (A/D Converter Data High Register) : 9FH
7
6
5
4
ADDM11
ADDM10
ADDM9
ADDM8
R
R
R
R
3
ADDM7
ADDL11
R
2
ADDM6
ADDL10
R
1
ADDM5
ADDL9
R
0
ADDM4
ADDL8
R
Initial value : xxH
ADDM[11:4]
ADDL[11:8]
MSB align, A/D Converter High Data (8-bit)
LSB align, A/D Converter High Data (4-bit)
ADCDRL (A/D Converter Data Low Register) : 9EH
7
6
5
4
ADDM3
ADDL7
ADDM2
ADDL6
ADDM1
ADDL5
ADDM0
ADDL4
R
R
R
R
3
ADDL3
R-
2
ADDL2
R
1
0
ADDL1
R
ADDL0
R
Initial value : xxH
ADDM[3:0]
ADDL[7:0]
MSB align, A/D Converter Low Data (4-bit)
LSB align, A/D Converter Low Data (8-bit)
ADCCRH (A/D Converter High Register) : 9DH
7
6
5
4
ADCIFR
–
TRIG2
TRIG1
R/W
–
R/W
R/W
3
TRIG0
R/W
2
ALIGN
R/W
1
0
CKSEL1
CKSEL0
R/W
R/W
Initial value : 00H
ADCIFR
TRIG[2:0]
ALIGN
CKSEL[1:0]
When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit,
write ‘0’ to this bit or auto clear by INT_ACK signal.
0
ADC Interrupt no generation
1
ADC Interrupt generation
A/D Trigger Signal Selection
TRIG2 TRIG1 TRIG0 Description
0
0
0
ADST
0
0
1
Timer 1 A match signal
0
1
0
Timer 4 overflow event signal
0
1
1
Timer 4 A match event signal
1
0
0
Timer 4 B match event signal
1
0
1
Timer 4 C match event signal
Other Values
Not used
A/D Converter data align selection.
0
MSB align (ADCDRH[7:0], ADCDRL[7:4])
1
LSB align (ADCRDH[3:0], ADCDRL[7:0])
A/D Converter Clock selection
CKSEL1 CKSEL0 Description
0
0
fx/1
0
1
fx/2
1
0
fx/4
1
1
fx/8
PS029902-0212
PRELIMINARY
183