Z51F3220FNX Datasheet, PDF (179/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
SPISR (SPI 2 Status Register) : B7H
7
6
5
4
SPIIFR
WCOL
SS_HIGH
–
R/W
R
R/W
–
3
FXCH
R/W
2
SSENA
R/W
1
0
–
–
–
–
Initial value : 00H
SPIIFR
WCOL
SS_HIGH
FXCH
SSENA
When SPI 2 Interrupt occurs, this bit becomes ‘1’. IF SPI 2 interrupt is
enable, this bit is auto cleared by INT_ACK signal. And if SPI 2 Interrupt
is disable, this bit is cleared when the status register SPISR is read, and
then access (read/write) the data register SPIDR
0
SPI 2 Interrupt no generation
1
SPI 2 Interrupt generation
This bit is set if any data are written to the data register SPIDR during
transfer. This bit is cleared when the status register SPISR is read, and
then access (read/write) the data register SPIDR
0
No collision
1
Collision
When the SS2 pin is configured as input, if “HIGH” signal comes into the
pin, this flag bit will be set.
0
Cleared when ‘0’ is written
1
No effect when ‘1’ is written
SPI 2 port function exchange control bit.
0
No effect
1
Exchange MOSI2 and MISO2 function
This bit controls the SS2 pin operation
0
Disable
1
Enable (The P17 should be a normal input)
PS029902-0212
PRELIMINARY
176