Z51F3220FNX Datasheet, PDF (277/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
12.5 Release Operation of STOP Mode
After STOP mode is released, the operation begins according to content of related interrupt register just before
STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is
released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt
service routine. Even if the IE.EA bit is cleared to ‘0’, the STOP mode is released by the interrupt of which the
interrupt enable flag is set to ‘1’.
SET PCON[7:0]
SET IEx.b
STOP Mode
Interrupt Request
Corresponding Interrupt
Enable Bit(IE, IE1, IE2, IE3)
N
IEx.b==1 ?
Y
STOP Mode
Release
Interrupt Service
Routine
Next Instruction
Figure 12.3 STOP Mode Release Flow
PS029902-0212
PRELIMINARY
275