Z51F3220FNX Datasheet, PDF (216/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
USI0DR (USI0 Data Register: For UART, SPI, and I2C mode) : E5H
7
6
5
4
3
2
USI0DR7 USI0DR 6 USI0DR 5 USI0DR 4 USI0DR 3 USI0DR 2
R/W
R/W
R/W
R/W
R/W
R/W
1
0
USI0DR 1 USI0DR 0
R/W
R/W
Initial value : 00H
USI0DR[7:0]
The USI0 transmit buffer and receive buffer share the same I/O
address with this DATA register. The transmit data buffer is the
destination for data written to the USI0DR register. Reading the
USI0DR register returns the contents of the receive buffer.
Write to this register only when the DRE0 flag is set. In SPI master
mode, the SCK clock is generated when data are written to this
register.
USI0SDHR (USI0 SDA Hold Time Register: For I2C mode) : E4H
7
6
5
4
3
USI0SDHR7 USI0SDHR6 USI0SDHR5 USI0SDHR 4 USI0SDHR 3
R/W
R/W
R/W
R/W
R/W
2
USI0SDHR 2
R/W
1
0
USI0SDHR 1 USI0SDHR 0
R/W
R/W
Initial value : 00H
USI0SDHR[7:0]
The register is used to control SDA0 output timing from the falling
edge of SCI in I2C mode.
NOTE) That SDA0 is changed after tSCLK X (USI0SDHR+2), in
master SDA 0 change in the middle of SCL0.
In slave mode, configure this register regarding the frequency of
SCL0 from master.
The SDA0 is changed after tsclk X (USI0SDHR+2) in master
mode. So, to insure operation in slave mode, the value
tSCLK X (USI0SDHR +2) must be smaller than the period of SCL.
USI0SCHR (USI0 SCL High Period Register: For I2C mode) : E7H
7
6
5
4
3
2
USI0SCHR7 USI0SCHR6 USI0SCHR5 USI0SCHR 4 USI0SCHR 3 USI0SCHR 2
R/W
R/W
R/W
R/W
R/W
R/W
1
0
USI0SCHR 1 USI0SCHR 0
R/W
R/W
Initial value : 00H
USI0SCHR[7:0]
This register defines the high period of SCL0 when it operates in
I2C master mode.
The base clock is SCLK, the system clock, and the period is
calculated by the formula: tSCLK X (4 X USI0SCHR +2) where
tSCLK is the period of SCLK.
So, the operating frequency of I2C master mode is calculated by the following equation.
fI2C =
1
tSCLK X (4 X (USI0SCLR + USI0SCHR + 4))
PS029902-0212
PRELIMINARY
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