Z51F3220FNX Datasheet, PDF (190/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

11.12.4 USI0 Clock Generation
Z51F3220
Product Specification
USI0BD
fSCLK
Prescaling
Up-Counter
(USI0BD+1)
/8
/2
SCLK
Sync Register
Edge
Detector
SCK0
CPOL0
/2
DBLS0
M
U
M
X
U
X
MASTER0
txclk
M
USI0MS[1:0]
U
X
M
U
rxclk
X
Figure 11.58 Clock Generation Block Diagram (USI0)
The clock generation logic generates the base clock for the transmitter and receiver. The USI0 supports four
modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous
and slave synchronous mode. The clock generation scheme for master SPI and slave SPI mode is the same as
master synchronous and slave synchronous operation mode. The USI0MS[1:0] bits in USI0CR1 register selects
asynchronous or synchronous operation. Asynchronous double speed mode is controlled by the DBLS0 bit in the
USI0CR2 register. The MASTER0 bit in USI0CR3 register controls whether the clock source is internal (master
mode, output pin) or external (slave mode, input pin). The SCK0 pin is active only when the USI0 operates in
synchronous or SPI mode.
Following table shows the equations for calculating the baud rate (in bps).
Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting
Operating Mode
Asynchronous Normal Mode (DBLS0=0)
Asynchronous Double Speed Mode (DBLS0=1)
Synchronous or SPI Master Mode
Equation for Calculating Baud Rate
Baud Rate
fx
16 USI0BD 1
Baud Rate
fx
8 USI0BD 1
Baud Rate
fx
2 USI0BD 1
PS029902-0212
PRELIMINARY
188