Z51F3220FNX Datasheet, PDF (205/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
Fast Device
SCLOUT
Slow Device
SCLOUT
SCL0
Wait High
Counting
Start High
Counting
High Counter
Reset
Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0)
Device1
DataOut
Arbitration Process
not adaped
Device2
DataOut
SDA0 on BUS
SCL0 on BUS
S
Device 1 loses
Arbitration
Device1 outputs
High
Figure 11.72 Arbitration Procedure of Two Masters (USI0)
11.12.20 USI0 I2C Operation
The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a
transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry
on other operations during a I2C byte transfer.
Note that when a I2C interrupt is generated, IIC0IFR flag in USI0CR4 register is set, it is cleared by writing an
any value to USI0ST2. When I2C interrupt occurs, the SCL0 line is hold LOW until writing any value to USI0ST2.
When the IIC0IFR flag is set, the USI0ST2 contains a value indicating the current state of the I2C bus. According
to the value in USI0ST2, software can decide what to do next.
I2C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode is
configured by a winning master. A more detailed explanation follows below.
PS029902-0212
PRELIMINARY
203