Z51F3220FNX Datasheet, PDF (102/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11. Peripheral Hardware
11.1 Clock Generator
11.1.1 Overview
As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to
be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The
main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT
pin, respectively. The main/sub clock can be also obtained from the external oscillator. In this case, it is
necessary to put the external clock signal into the XIN/SXIN pin and open the XOUT/SXOUT pin. The default
system clock is 1MHz INT-RC Oscillator and the default division rate is eight. In order to stabilize system
internally, it is used 1MHz INT-RC oscillator on POR.
- Calibrated Internal RC Oscillator (16 MHz )
. INT-RC OSC/1 (16 MHz)
. INT-RC OSC/2 (8 MHz)
. INT-RC OSC/4 (4 MHz)
. INT-RC OSC/8 (2 MHz)
. INT-RC OSC/16 (1 MHz, Default system clock)
. INT-RC OSC/32 (0.5 MHz)
- Main Crystal Oscillator (0.4~12 MHz)
- Sub Crystal Oscillator (32.768 kHz)
- Internal WDTRC Oscillator (5 kHz)
11.1.2 Block Diagram
XIN
XOUT
STOP Mode
XCLKE
STOP Mode
IRCE
SXIN
SXOUT
STOP Mode
SCLKE
Main OSC
fXIN
Internal RC OSC
(16MHz)
IRCS[2:0]
3
1 /1
1 /2
1 /4
1 /8
1/16
1/32
M
U ^fIRC
X
Clock
Change
Sub OSC
fSUB
2
SCLK[1:0]
WT
DCLK
System
Clock Gen.
SCLK (fx)
(Core, System,
Peripheral )
BITCK[1:0 ]
2
fx/4096
fx/1024
fx/128
fx/16
M _{BIT clock}
U
X
WDTRC OSC
(5kHz)
Stabilization Time
Generation
BIT
overflow _{WDT clock}
BIT
M
U
X
/256
WDT
WDTCK
Figure 11.1 Clock Generator Block Diagram
PS029902-0212
PRELIMINARY
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